何为全速测试(at speed test)？在工艺节点在130nm以下的时候，很多情形下的物理缺陷都是由于延时来引起的。因此在对这种类型的chip做dft的时候，需要建立一个新的故障模型，业内称之为延时故障模型（time delay model）。解决的方法就是全速测试，所谓的全速测试就是让芯片工作在自己高倍时钟频率上，这个频率往往是要高过ATE的时钟的。
这样对扫描模型的建立就提出了新的要求。即至少要保证芯片的latch clock和capture clock为芯片内部的高倍时钟。
synopsys对此种问题的解决方法就是OCC（on chip clocking）。OCC/OPCG的基本原理是在 scan shift 模式下， 选择慢速的ATE 时钟，load 或 unload 扫描链；在 capture 模式下，对 free-running PLL clock 过滤筛选出 lauch 和 capture clock 进行at-speed 测试 。
在做SCAN的时候，由于ATE时钟速度和芯片port的传输速度的限制，导致ATE无法向片传输高速时钟。但是，芯片内部需要 进行At Speed 测试的时候，用到和system mode一致的时钟频率进行测试。此时，需要由芯片内部自己产生测试时钟。
这个是典型的OCC(On Chip Clock)电路。主要有两部分组成，一个是occ controller，另外一个是clock chain。
1. DFT Compiler自动插入。
2. 手动编写OCC 的verilog 电路，在dft_insert阶段。
如果不稍加引导工具来做tree，本案例工具长出来的tree一定会把occ那路时钟和function clk做balance。而本来occ那路时钟其实可以做的比较短。occ那路时钟被拖长之后就会有一系列的问题，比如绕线问题，比如clock chain中reg到occ controller中reg的hold timing问题等等。
Field programmable gate array is an IC which contain logic gates with programmable interconnection.In this the program is does't built during the production.These are field programmable because they can be configured by the user after manufacturing.It contain an array of programmable logic blocks.The logic blocks can be configured to perform combinational functions.It also include memory elements (flip flop or block of memory).It is configured by HDL (hardware description language) similar to that ASIC.
Advantages of FPGA:-
Disadvantages of FPGA:-
Advantages of ASIC:-
Disadvantages of ASIC:-
Difference between FPGA and ASIC:-
Q 1.What are the types in physical verification?
A. LVS (layout vs schematic).
DRC (design rule constrain check).
ERC (electric rule check).
LEC (logical equivalence check).
Q 2.How to fix setup and hold violations at a time?
A. It is not possible to fix both at a time because if we increase the delay in data path it's good for hold and bad for setup.But there is only one way to fix it.
Q 3.How can you avoid cross-talk?
A. a) Increase the spacing between the aggressor and victim nets.
c) Maintain the stable supply.
d) Increase the drive strength of cell.
e) Layer jumping.
f) Victim net width increasing then resistance decreases.
g) Guard ring.
h) Cell sizing (up sizing).
Q 4.What is cross-talk?
A. It is the process of re connecting the scan chains in the design to optimize for routing by reordering the scan chain connection which improves timing and congestion.
Q 6.What is the concept of rows in the floor plan?
A. The std-cells in the design are placed in rows.All rows have equal height and spacing.The width of the row can vary.The std-cell in the row get the power and ground connection from vdd and vss rails.Sometimes technology allows the rows to be flip.So they can share the power and ground rails in vdd-vss-vdd patron.
Q 7.What are the advantages of NDR's?
A. a) By applying the double width we can avoid the EM.
b) By applying double spacing we can avoid the cross-talk.
c) Help's to avoid congestion at lower metal layer.
d) Help's pin accessibility of std-cells .
Q 8.What is temperature inversion?
A. At higher CMOS technologies cell delay increases when temperature increases.But when you are in lower technologies i.e below 65nm cell delay has inversely proportional to temperature.
Q 9.In reg to reg path if you have setup problem where will you insert buffer?
A. We can insert buffer near to launch flop which decreases the transition time.Hence decreasing the wire delay therefore overall delay will decrease.When arrival time will decrease setup violations will reduce(required time-arrival time).
Q 10.What is partitioning?
A. It is the process of dividing the chip into small blocks this is done mainly to separate different functional blocks and also make placement.routing easier.
Q 11.How can you reduce dynamic power?
A. a) Reduce power supply voltage.
b) Reduce voltage swing in all nodes.
c) Reduce the switching probability (transition factor).
d) Reduce load capacitance.
Q 12. Why double via insertion?
A. To reduce the yield loss due to via failures,double via's are inserted traditionally double via's where inserted in post route and then modify the routing to fix any DRC's.
Q 13.What is metal fill insertion?
A. At the time of etching they use some type of chemicals due to that chemical metal loss will be more for that reaction we are inserting the metal fills.
Q 14.What is metal slotting?
A. It is the Technic for avoiding the problems like metal lift off and metal erosion.
Q 15.What are the power dissipation components?
A. Dynamic power consumption:- Occurs when signals which go through the CMOS circuit change there logic state by charging discharging of o/p node capacitor.
static (leakage power consumption):- It is the power consumed by the sub threshold currents and by reverse biased diodes in a CMOS transistor.
short circuit power consumption:- It occurs during switching on both the NMOS and PMOS transistors in the circuit and they conduct simultaneously for a short amount of time.
Q 16.What is dishing effect?
A. It is defined as the difference between the height of the oxide in the spaces and that of the metal in the trenches.It is caused by CMP.It may reduced by some dummy fill Technics effectively.
Q 17.What is CMP (chemical mechanical polishing)?
A. It is the process of smoothing surface with the combination of chemical and mechanical forces.It is used in IC fabrication to get a high level of polarization.
Q 18.What is the use of placement blockage?
A. a) Defines std-cell and macro area.
b) Reserve channels for buffer insertion.
c) Prevent cells from being placed at or near macros.
d) Prevent congestion near macros.
Q 19.What are the types of global routing?
A. a) Time driven global routing.
b) Cross-talk driven global routing.
c) Incremental global routing.
Q 20.What are the violations solved in LVS?
A. a) Shorts.
c) Missing text layers.
d) Missing lib in GDS.
e) Missing soft layers.
Q 21.What is the clock latency?
A.It is the delay between the clock source and clock pin.It is two types.Clock source latency and clock network latency.The time taken from clock source to definition pin is the clock source latency and from the clock definition pin to clock pin of the flip flop 2 is the clock network latency.
Q 22.How to fix setup and hold violations?
Q 24.What are the outputs of floor plan?
Q 25.What is keep-out margin?
A. It is the region around the boundary of fixed macros in design in which no other macros or standard cells not allows.It allows only buffers and inverters in it's area.
Q 26.How will you synthesize clock tree?
A.a) Single clock-normal synthesis and optimization.
b) Multiple clocks-synthesis each clock separately.
c) Multiple clocks with domine crossing synthesis each clock separately and balance the skew.
Q 27.What is IR drop?
A. Each metal layer has a resistance value.When the current flows through the metal the resistance consumes some current.This is the IR drop.If the resistance is more the drop also more.
Q 28.how to reduce power dissipation using HVT and LVT in the design?
A.If we have positive slack use HVT cells in the path and use LVT cells in the path when we have negative slack.HVT cells have large delay and less leakage power. LVT cells have less delay and more leakage power.To meet the timing use LVT cells and to reduce the leakage power use HVT cells.
Q 29.What is wire load model (WLM)?
A. It is an estimation of delay based on area and fan-out.The delay depend on..
Area of the nets.
Q 30.What is signal integrity?
A. It is the ability of an electric signal to carry information reliably and to resist the effects (cross-talk, EM) of high frequency electromagnetic interface from near by signals.
Q 31.Doe's cross-talk always cause violations?
A.Yes it is because cross-talk adds or subtracts energy to the signal which cause setup or hold violations.
Q 32.How a positive or negative edge triggered flip flop will effect the setup and hold violations?
A. Positive edge triggered flip flop will favour to setup (setup violations will reduce).Negative edge triggered flip flop will favour to hold (hold violations will reduce).
Q 33.What are the i/p's and o/p's of power planing?
Q 34.What are the i/p's and o/p's of placement?
Q 35.If we increase the fan-out of the cell how it will effects delay?
A. Fan-out lead to increased capacitive load on the driving gate.Therefore longer propagation delay.
Q 36.What is multi driven nets?
A. It can be created in RTL by introducing drivers of same or different signal strengths.However during a net with multiple signals are not considered as a good practice.This could lead to failure in a post silicon verification as the driver strength can potentially get heavily altered during manufacturing defects.Many EDA tools don't allow multi driven nets in the design and the designers are expected to remove all multi driven nets from the design.
Q 37.What is magnetic placement?
A. To improve the timing for the design or to improve the congestion for a complex floor plan we can use magnetic placement to specify fixed objects as magnets and icc moves their connected standard cells close to them.For the best results perform the magnetic placement before standard cells are placed.
Q 38.What is lookup table?
A.The table is drawn by using input transition and output load values.It is used to calculate the cell delay.
Q 39.What does we do for low power design?
A. We apply low power techniques
Q 40.What are the types of checks done in prime time?
A. a) Timing (setup,hold,transition).
b) Design constraints.
e) Clock skew.
Q 41.What analysis we do during floor plan?
A.a) Overlapping of macros.
b) Allowable IR drop.
c) Global route congestion.
d) Physical information of the design.
Q 42. What are the different types of delay models?
A. a) WLM (wire load model)
b) NLDM ( non linear delay model)
c) CCS (composite current source)
Q 43.Where placement blockage is created?
A. At floor plan stage it acts like guidelines for placement of standard cells.In CTS stage in order to balance the skew more no.of buffers and inverters are added and blockages are used to reserve space for buffer and inverter.
Q 44.Why we apply NDR's in placement?
A. Applying NDR's in placement because of avoiding congestion and timing problem.These problems are difficult to fix at routing.These are special rules like double spacing and double width.
Q 45.What is mesh?
A. The horizontal and vertical power straps in the design are called mesh.
Q 46.Why I/O cells are placed in the design?
A. The i/o cells are the one which interact in between the blocks outside of the chip to internal blocks of the chip.In floor plan stage i/o cells are placed in between core and die.These are responsible for providing voltage to the cell in the core.
Q 47.What are the complex cells in the floor plan?
A.These are the cells which are made of group of std-cells based on functionality requirement.This cells height is grater than the std-cells and lesser than the macros.
Q 48.How to fix Electromigration (EM)?
A. a) Down size the driver.
b) Increase the metal width.
c) Add more vias.
d) Spread cells.
Q 49.What is etching?
A.It is used in micro-fabrication to chemically remove layers from the surface of the wafer during manufacturing.
Q 50.What is SOI technology?
A.It refers to use of layered silicon insulator.It reduces leakage current and lower power consumption.
Q 51.What is aggressor and victim?
A.these two terms will come in cross-talk concept.
Aggressor:- A net which create the effect on nearer net(victim).
victim:- A net which receives the effect from nearer net(aggressor).
Q 52. What is Mealy and Moore?
A. Mealy:- The outputs are depends on input and present state.
Moore:- The outputs are depends on only present state.
A. The physical design is the process of transforming a circuit description into the physical layout which describes position of the cells and routs for the interconnections between them.
Q 2.which design is more complicated 10MHZ or 100MHz?
A. 100mhz. because high frequency means low time period.So it is difficult to handle the violations in low time period.
Q 3.what is floor planing?
A. The floor plan is a process of determining the macro placement,power grid generation and I/O placement.
Q 4.If you have both IR drop and congestion how will you fix it?
A. a) Spreed macros.
b) Spreed standard cells.
c) Increase strap width.
d) Increase no.of straps.
e) Use proper blockage.
Q 5.What are the Tie-high and Tie-low cells?
A. These are used to connect the gate of transistor to either power or ground.It avoid direct connection between power and gate of transistor.
Tie-high:- One terminal is connected to vdd and another terminal is connected to gate of transistor.
Tie-low:- One terminal is connected to vss and another terminal is connected to gate of transistor.
Q 6.What are the checks to be done before cts?
A. a) Placement -completed.
b) Power ground nets -pre-routed.
c) Estimated congestion -acceptable.
d) Estimated timing -acceptable.
e) Estimated max transition/capacitance -no violations.
f) High fan-out nets.
Q 7.What are the power gating cells?
A. The power gating is to avoid static power dissipation.The power gating cells are
a) Power switches.
b) Level sifters.
c) Retention registers.
d) Isolation cells.
e) Power controller.
Q 8.What is HFNS(high fan-out net synthesis)?
A. HFNS is the process of buffering the high fan-out nets to balance the load.
Q 9.Where HFNS is used?
A. Generally at placement stage HFNS is performed.it is also performed at synthesis step using design compiler.
Q 10.What is Electromigration(EM)?
A. When high current density continuously flows through a metal due to the high current the atoms moving with kinetic energy and they transfer the energy to another atoms and increases the temperature due to these the metal will damage.
Q 11.Is zero skew is possible?
A. Practically it is not possible because all the flip flops are not getting the same clock.The skew is exist when the two different clocks are present.Zero skew means all clocks are same practically it is not possible.
Q 12.How to reduce latchup problem?
A. a) Increase spacing between p-well and n-well.
b) Increase well/substrate doping concentration.
c) Use ground rings around device.
Q 13.What are the check list after cts?
A. a) Skew report.
b) Clock tree report.
c) Timing reports for setup and hold.
d) Power and area report.
Q 14.What is synthesis?
A. It is a process to convert RTL code into design implementation.
Q 15.which metal layer will be used for clock in 7 metal layer design.why?
A. Metal 4 and 5.because the clock nets will consume 30 to 40% of power in the design.So to reduce the IR drop we are using low resistance metal.top 6,7 metal layers for power connection and 5,4 for clock nets.
Q 16.What is antenna effect?
A. Increasing net length can accumulate more changes while manufacturing of the device due to the ionization process.If this net is connected to gate of the MOSFET it can damage dielectric property of gate and causing damage to MOSFET.
Q 17.What is cloning and buffering?
A. Cloning:-it is a method of optimization that decrease the load of heavily loaded cell by replacing the cell.
Buffering:-it is a method of optimization that is used to insert buffer in high fan out nets to decrease the delay.
Q 18.Why NAND gate is preferred than NOR?
A. At transistor level the mobility of electrons is normally three times that of holes compared to nor and NAND gate is faster,less leakage.
Q 19.What is LVS(layout vs schematic)?
A. It is a class of EDA software that determines whether a particular IC layout corresponds to the original schematic of design.
Q 20.What is shielding?
A. Placing ground net in between aggressor and victim nets then voltage discharge on ground net.This will reduce the cross-talk.
Q 21.What is isolation cell?
A. These are special cells required at the interface between blocks which are shutdown and always on.It is necessary to isolate the floating inputs.
Q 22.What is retention flop?
A. These cells are special flops with multiple power supply.When design blocks are switched off for sleep mode data in all flip flop contained desires to retain state for this retention flops must be used.
Q 23.What are the i/p required for CTS?
A. a) Detailed placement database.
b) Target for latency and skew if specified.
c) Buffers or inverters to build the clock tree.
d) NDR rules.
e) Clock tree DRC's.
Q 24.What are the CTS goals?
A. a) Minimize clock skew.
b) Minimize insertion delay.
c) Minimize power dissipation.
Q 25.What are the effects of CTS?
A. a) Clock buffers are added.
b) Congestion may increase.
c) Non-clock cells may have been moved to less ideal location.
d) Can introduces timing and max transition/capacitance violations.
Q 26.What are the different types of cells?
A. Tap cell:- These are used to avoid latch up problem.
End cap cells:- These are placed at the edges to avoid cell damage at the end of the row.
Decap cells:- These are placed between power rail and ground rail to avoid dynamic IR drop.
Filler cells:- These are used to connect the gap between the cells.
ICG cells:- Clock gating cell to avoid dynamic power dissipation.
Pad cells:- To interface with outside devices.i/p to power,clock pins are connected to pad cells and out side also.
JTAG cells:- These are used to check IO connectivity.
Q 27.Why HFNS (high fanout net synthesis)?
A. To balance the load HFNS is performed.too many loads will effects the delay numbers and transition time.Because load is directly proportional to load.By buffering the HFNS the load can be balanced.
Q 28.What is hard macro?
A. The circuit is fixed and we don't know which type of gates using inside.We know only timing information not the functional information.
Q 29.What is soft macro?
A. The circuit is not fixed and we know which type of gates using inside.We know timing information and also functional information.
Q 30.What is the formula for distance between macros?
A. Distance between macros = no.of pins * pitch / total layers.
Q 31.What is CTO(clock tree optimization)?
A. It improves the clock skew and clock insertion delay by applying additional optimization. CTO is performed during clock_opt process.
Q 32.What is the deference between normal buffer and clock buffer?
A. Clock buffer having equal rise and fall time but normal buffer not like that.Clock buffers are usually designed such that an i/p signal with 50% duty cycle produces an o/p with 50% duty cycle.
Q 33.Why should we solve setup violations before CTS and hold violations after CTS?
A. Setup violations depends on data path while hold violations depends on clock path.Before CTS clock path is taken as ideal because we don't have skew and transition numbers of the clock path but this information is sufficient to perform setup analysis.Clock is propagated after CTS that's why hold violations are fixed after CTS.
Q 34.What is global routing?
A. It is done to provide instructions to the detailed router about route every net.It provides the channels for interconnect to be routed.
Q 35.What is detailed routing?
A. It is where we specify the exact location of the wires/inter connects in channels specified by the global routing.Metal layer information of the interconnects are also specified here.
Q 36.What is the use of virtual clock?
A. It will help to reduce the time delay of the overall operation.It is logically not connected to any pin of design and physically does't exist.
Q 37. What is MMMC(multi mode multi corner)?
A. It is a combination of mode and corner that is required for a particular timing check such as setup and hold.
Q 38.What is the difference between hierarchical design and flat design?
A. Hierarchical design has blocks and sub blocks in an hierarchy.Flat design has no sub blocks and it has only leaf cells. Hierarchical design takes more run time and flat design takes less run time.
Q 39.During power analysis if you are facing IR drop problem then how did you avoid?
A. a) Increase power metal layer width.
b) Go for high metal layer.
c) Spread macros or standard cells.
d) Provide more straps.
Q 40.What are the types of routing?
A. a) Global routing.
b) Track assignment.
c) Detailed routing.
d) Search and repair.
Q 41.What is body effect?
A. It is the change in threshold voltage resulting from a voltage difference between the transistor and body.These is caused by body biasing.
Q 42.What is glitch?
A. Glitch is a electric pulse of short duration that is usually the result of fault or design error.
Q 43.What are the benefits of SOI technology?
A. a) Low parasitic capacitance.
b) High peed performance.
c) Reduce short channel effects.
d) No latch up.
e) Low threshold.
Q 44.What are the guidelines for macro placement?
A. Fly-lines,port communication,macros are placed at boundaries,spacing between macros,macro grouping,macro alignment,notches avoiding,orientation,blockages,avoid crisscross placement of macros.
Q 45.What are the sanity checks in pd?
A. a) Check_library.
Q 46.What is the difference between Halo and Blockage?
A. Halo:- It is the region around the boundary of fixed macros in design in which no other macros or standard cells can be place.If macros moves halo will also move.
Blockage:- It can be specified for any part of the design.If we move the block blockage will not move.
Q 47.Why we apply NDR rules before routing?
A. Some times with default routing it is very hard to avoid cross talk,electromigration.Fixing the cross-talk,electromigration in routing stage is difficult.So we are applying ndr rules(double space,double width) before routing.
Q 48.What are the types of blockages?
A. Hard blockage:- It does't allow inverters,buffers,standard cells.
Soft blockage:- It allows only inverters and buffers and blocks standard cells.
Partial blockage:- It will allow both buffers and standard cell in a percentage value.
Q 49.What is congestion?
A. When the available tracks are less than the required tracks this effect will occur.When the signals are more than the tracks then congestion will occur.
Q 50.How to fix congestion?
The delay values of IC will varies in different conditions like changing in processor,voltage,temperature(PVT).The delay value of IC in cold weather is different and in hot weather is different.In cold weather the metals in IC will shrink.In hot weather the metal will expand so the delay will increase.To over come this effect flat derate(delay) is applied in the circuit.
In simple words OCV is a technique in this flat derate is applied to make faster path more fast and slower path more slow.Delays varies across a single die due to PVT(processor,voltage,temperature).This need to be modeled by scaling the coefficients.
CRPR (clock re convergence pessimism removal):-
In this concept we removes the pessimism and derate to the common path.Generally we add the delay to every buffer in the process of OCV. But adding more delay is also effect the speed of the chip and it may cause violations to over come this we are removing the delay to the common path in the process of CRPR.
In simple words It can be used to remove the pessimism and penalty by using common cell for both launch and capture flip flop.
It is a functional verification of RTL design.After the RTL design by applying test cases we verify the design in verification stage.If any mistakes are found then the design is re send to the RTL designing department.The verification stage will take nearly 60% of the total time.Performing this verification at this stage is most advantageous because correcting the faults at routing stage is difficult and takes more time.
It is a process of converting the RTL code into gate level netlist.Up to RTL verification the design is technology independent.In synthesys process the design is converted into technology dependent.it is 3 stage process.
1.Translation:- The RTL code is converted in to Boolean expression.
2.Optimization:- In this stage Boolean expression is optimized by SOP and POS optimization method.
3.Mapping:- In this technology independent Boolean expression is converted into technology dependent and generates the gate level net list.
The inputs for synthesis are RTL code, .SDC and .LIB.after the synthesis the generated outputs are gate level netlist and .SDC.
Design for testability(DFT) is a technique which facilitates a design to become testable after production.In this stage we put extra logic along with the design logic during implementation process which helps post production process.The DFT will make the testing easy at post production process.At this stage an ATPG(automatic test pattern generator) file will generated.
The floorplan is the process of determining the macro placement,power grid generation and i/o placement.It is the process of placing blocks/macros in the chip/core area there by determining routing areas between them.It determines the size of the die and creates wire tracks for placement of standard cells.It creates power straps and specifies pg connection.It also determine the i/o ,pin/pad placement information.
Placement is the process of automatically assigning correct position to standard cells on the chip with no overlapping.By global placement outside of standard cells will placed inside roughly.By the detailed placement the standard cells will place in site rows(legalize placement).In placement stage we check the congestion value by GRC map.
In this stage we built the clock tree by using inverters and buffers.In the chip clock signal is essential to the flip flops,to give the clock signal from clock source we built the clock tree.It is the process of balancing the clock skew and minimizing insertion delay in order to meet timing and power.
Before the routing stage the connection between the macros,standard cells,clock,i/o port are logical connections.In this stage we connect all the cells physically with the metal straps.Routing is divided as two parts 1)global routing 2)detailed routing.The global routing will tell for which signal which metal layer is used.Before the detailed routing all are the logical connections.In detailed routing the physical connections are done.
After the routing the physical layout of chip is completed.In signoff stage all the tests are done to check the quality and performance of the layout before tapeout.After this the design is converted into GDS II file.
By the GDS II file information we fabricate the chip.The total design is converted into chip by the manufacturing process.
Packaging and testing:-
After the fabrication process we test the chip.If there is any fault in the design then we modifies the design by repeating the steps.If there are no faults then chip will go to packaging.
静态时序分析（Static Timing Analysis, 以下统一简称STA）是验证亚博app下載集成电路时序是否合格的一种方法，其中需要进行大量的亚博app下載计算，需要依靠工具进行，但是我们必须了解其中的原理。在综合工具（DC/Genus 等），布局布线工具（ICC2/Innovus 等），时序分析工具（PrimeTime/Tempus 等）中都嵌入了不同的STA引擎，这些引擎往往在时间和精度方面有一些折衷，但是目的就是以尽量小的误差去模拟物理器件和绕线的SPICE模型，从而更接近芯片生产出来后真实的性能。
1.星主，请问一下，icc2里面做完cts，clock上面的net跟cell是默认为dont touch的吗？ 还有useful skew(ccd)可用于build cts(非opt阶段)阶段吗？CCD使用有何注意事项？
ICG的ck pin在长tree时是through pin，它的clock tree latency相比其他sink点比如会短一些。因此大部分情况需要将ICG靠leaf端摆放。然而从功耗角度，ICG是越靠root端会越省功耗，因此这是一个矛盾体，在设计实现时需要有一个tradeoff。
Clock gating setup常见的解决方法: 加大gating check的值，加大data path的优化力度（data层面）；人工调整ICG的clock tree。
在跑PR flow过程中，务必加上antenna rule，这样在绕线过程中工具可以根据看到的violation来进行antenna violation的auto fixing。这里再强调下，能够让工具自动处理的工作，千万别自己做（比如DRC Fixing）。
插diode的命令没有问题。核心是ICC能否看到antenna violation?如果看不到antenna violation，不插diode才是工具正常的behavior。如果calibre中发现有这类violation，则可以通过改变antenna rule中的mode和ratio值来加紧约束，让PR工具能够看到violation，从而进行auto fixing。
星主，请教个问题 在upf flow中，always on net,比如iso cell的控制信号，power switch 的控制信号，是否需要做特殊处理。怎么能够保证工具一定用always on cell来优化，谢谢啦！提问：
【点评】ISO Cell是放置在相对ON的Domain，因此iso cell的控制信号正常解高fanout即可，插入的buffer直接用普通buffer即可。
Power Switch Cell的控制信号，比如req和ack信号，这个就需要特别注意了。因为当前的设计是做power domain的，而ack，req这些信号，如果中间需要插buffer，需要插always on buffer。为了避免这种麻烦，power switch cell 控制信号的链要串好点，相邻两个要足够近，确保没有max transition的问题。
【思考题】：在实际项目中，往往会将所有Power Switch Cell串成一条或若干条链，为什么要这么做？
4.提问：星主好，请教下带有isolation 功能的levelshift。比如是一个1.8转3.3的，1.8可以关断。3.3是always on的。请问这种level shift 1.8能不能关断。需不需要额外给一个always on 的1.8v电源？
【点评】这种应用场景，加带isolation功能的level shifter即可。Level Shifter主要有两种类型，一种是普通的level shifter（LS），另外一种是带isolation功能的enable level shifter（ELS）。
以下图为例，0.9V Domain A为一个需要做power gating的domain。1.1V Domain为一个AO Domain。当信号从A domain出来要到B domain时，需要在output端加ELS，当信号从B domain要到A domain时，只需插LS即可。
那么，ELS和LS应该摆放在哪里呢？是摆放在source端还是destination端？（也称之为source side和sink side）答案是都可以，它和level shifter的选型密切相关。在亚博app下載后端实现时，可以选用便于powerplan规划的level shifter。
5.提问：前辈，T28工艺，signoff recommend 中margin type类提到flop hold constraints uncertainty, 利用传统Flat ocv 则不用额外考虑；如果用SBOCV 则需要额外增加？为什么？谢谢
这种情况是预防flop的hold margin不够导致芯片fail。如果用flat ocv，是使用统一的derate，一般比较悲观，所以margin够。在先进工艺节点，很多时候foundary或者vendor其实会提供一种叫SCM（Statistical Constraint Margining）的库，ARM一般都会提供一套这样的库。